1. Field of the Invention
This invention relates to an architecture, circuitry and method for operating a subsystem through a test access port (“TAP”), preferably the JTAG access port described in IEEE Std. 1149.1. The subsystem includes one or more circuits that derive control from a shift register. The shift register can be a part of or separate from the subsystem, and the shift register can be written to via the serial input pin of the TAP and read from via the serial output pin of the TAP.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
In early the 1990's, a standard was developed and approved as IEEE Std. 1149.1, henceforth referred to “the Joint Test Action Group” (JTAG) standard. The JTAG standard was envisioned to allow testing of the integrated circuit after it had been assembled onto a printed circuit board. For example, multiple integrated circuits may be solder bonded to a printed circuit board, where it is desirable to test an entire electronic subsystem of multiple integrated circuits after those integrated circuits have been solder bonded to the board. The JTAG standard provided for testing numerous integrated circuits which make up an electronic subsystem while those circuits are electrically coupled to the board. The JTAG standard can, therefore, test not only the operation of multiple integrated circuits, but the interconnection of those circuits to the printed conductors of the board.
In order to test a circuit using the JTAG standard, it is important that the circuit be JTAG compliant. Specifically, the circuit must have a JTAG test access port (“TAP”). Through the TAP, the JTAG compliant integrated circuit can be tested using only four signals: a serial input signal (TDI), a serial output signal (ISDO), a clock signal (TCK), and a mode select signal (TMS). Each integrated circuit to be tested must, therefore, have a JTAG-type TAP for receiving a serial bitstream controlled by the clock and mode select signals and, in accordance with the test response, produce a serial bitstream output, all of which take place on a maximum four conductors that interface with the TAP placed internal to the JTAG compliant integrated circuit. There are various ways in which to utilize the TAP. For example, a boundary scan mechanism may be used to test one or more boundary scan cells arranged about the peripheral of each JTAG-compliant circuit. The TAP controller is used for orchestrating signal flow within and through each of the cells.
FIG. 1 illustrates an electronic subsystem 10 embodied upon possibly multiple printed circuit boards 12a and 12b. Each board 12 may have multiple integrated circuits mounted thereon. In the example provided, board 12a has two integrated circuits 14 and 16 electrically coupled to trace conductors which extend within and/or upon the planar surfaces of board 12a. For sake of brevity, only two integrated circuits are shown on board 12a. However, it is recognized that a printed circuit board may embody certainly more than two integrated circuits. Printed circuit board 12a also shows an edge connector 18 that contains multiple contacts 20. Four contacts can be reserved to receive four signals from the host computer, or automated test equipment (“ATE”), shown as reference numeral 24.
Host computer preferably contains a memory into which a test language can be stored. Preferably, the test language is one that is platform-independent, i.e., a language that is independent of the operating system of the host computer. A popular test language specifically tailored to test JTAG compliant integrated circuits based on the IEEE 1149.1 standard is the JAM™ Standard Test and Programming Language (STAPL). STAPL consists of source code that is executed directly by the interpreter program, without being first compiled into binary executable code. Information regarding the STAPL language can be obtained from Altera Corp., San Jose, Calif.
STAPL, executable by host 24, produces instructions and data as a serial bitstream, and forwards that bitstream as the TDI signal. The processor within host 24 can also produce a clock signal and a mode select signal, TCK and TMS. The clocking and mode select signals can be broadcast to corresponding pairs of input pins on each integrated circuit 14 and 16, whereas the serial bitstream is placed in one pin, and daisychained through, for example, boundary scan cells 26 of each integrated circuit, among all integrated circuits linked between TDI and TDO edge connectors 20 of board 12a. This process can be repeated by interconnecting multiple boards, whereby the TDO output from board 12a can be forwarded to the TDI input of board 12b to ensure integrated circuits on one board are daisy-chained together with integrated circuits on another board, all of which form an electronic subcomponent.
The IEEE Std. 1149.1 specification provides for the daisy-chained interconnection of multiple boundary scan cells 26, whereby the sequence of bits within the serial bitstream are loaded into corresponding elements 26 so they can then be parallel-fed into the core logic 28 and 30 of corresponding integrated circuits 14 and 16. In this fashion, a test vector represented as a sequence of 1 s and 0 s can be loaded into core logic 28 and 30 and, subsequently, based on the status of the clock and mode select signals, the response of a test vector can be read serially from core logic 28 and 30 via the serial output TDO.
The platform-independent programming language that interfaces with JTAGcompliant integrated circuits is specifically tailored not only to test the core logic of integrated circuits, but can also be used to program one or more integrated circuits. Thus, the integrated circuits can include Programmable Logic Devices (PLDs) such as those manufactured by Cypress Semiconductor Corp. Using JTAG compliant integrated circuits and software specifically written to program such integrated circuits via the four-pin TAP interface poses a significant advantage in the integrated circuit manufacturing industry. It would be desirable to maintain the well-known, four-conductor JTAG interface and JTAG-specific programming languages for JTAG-complaint circuits, yet it would be further desirable to be able to test and/or program integrated circuits which are not JTAG compliant. For example, the automated test equipment may be located a considerable distance from the electronic subcomponent. In this instance, a serial link is needed, such as that found in the JTAG interface. However, there may be one or more integrated circuits on the printed circuit board that are not JTAG compliant. Such integrated circuits would, therefore, not have a TAP, nor could such circuits recognize the clock signal and mode select signal protocol of a JTAG four-pin bus.
It may be of further benefit to not only test, but to control an electronic subsystem using the JTAG interface. Such control would desirably include sending JTAG control signals from the host computer to the electronic subsystem, a portion of which may involve an integrated circuit that is not JTAG compliant. As defined herein, an integrated circuit which is not JTAG compliant is one that does not have a TAP and does not recognize or place any significance to the JTAG clock signal and mode select signal, or any instructions contained within the serial bitstream of TDI.